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motorola semiconductor techical data rev 1.5 9/99 ? motorola, inc. 1999 high speed graphic monitor on-screen display - 16 cmos this is a high performance hcmos device designed to interface with a micro controller unit to allow colored symbols or characters to be displayed onto crt monitor. because of the large number of fonts, 256 fonts including 240 standard fonts and 16 mulit-color fonts, hsgmosd-16 is suitable to be adopted for the multi-language monitor application especially. its on-chip pll allows both multiscan operation and self generation of system timing. it also minimizes the mcu?s burden through its built-in ram. by storing a full screen of data and control information, this device has a capability to carry out ?screen- refresh? without any mcu supervision. since there is no clearance between characters, special graphics oriented characters can be generated by combining two or more character blocks. there are two kinds of resolutions that users can choose. by changing the number of dots per horizontal line to 384 (cga) or 768 (svga), smaller characters with higher resolution can be easily achieved. the full osd menu is formed of 15 rows x 30 columns which can by freely positioned on anywhere of the monitor screen by changing vertical or horizontal delay. special functions such as character background color, blinking, bordering or shadowing, four-level windows with programmable shadowing, row double height and double width, programmable vertical height of character and row-to- row spacing, and full-screen erasing and fade-in/fade-out are also incorpo- rated. there are 8 color selections for any individual character display with row intensity attribute and window intensity attribute to expand the color mixture on osd menu. ? wide operating frequency range for high end monitor: max. 135khz ? totally 256 fonts including 240 standard fonts and 16 multi-color fonts. ? two resolutions: 384 (cga) or 768 (svga) dots/line ? fully programmable character array of 15 rows by 30 columns ? 8-color selection for characters with color intensity attribute on each row ? 7-color selection for characters background ? true 16-color selection for windows ? fancy fade-in/fade-out effects ? programmable height of character to meet multi-sync requirement ? row to row spacing control to avoid expansion distortion ? four programmable windows with overlapping capability ? shadowing on windows with programmable shadow width/height ? character bordering or shadowing ? character/symbol blinking function ? programmable vertical and horizontal positioning for display centre ? double character height and double character width ? internal pll generates a wide-ranged system clock (104 mhz) ? m_bus (iic) interface with address $7a (spi bus is mask option) MC141545P2C ordering information MC141545P2C plastic dip pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 fbkg b g r v ss v dd vflb v dd(a) rp vco scl(sck) sda(mosi) ss hflb v ss(a) int p suffix plastic package case 648-08
MC141545P2C 2 motorola block diagram 11 i n t f b k g vflb sda(mosi) 9 display data receiver bus arbitration vertical control circuit horizontal control background generator colour encoder 12 bits shift registers character row buffer logic waddr wcolour and ccolours and select chs cws wcolour and control ccolours and select w a d d r sc hord cclk d h o r lp 4 12 b l a c k e d g e verd mclk rp vco hflb scl(sck) ss data rfg addrc 6 y 9 8 7 8 6 8 3 2 5 v dd v ss 16 54 15 14 13 12 3 w r 4 chs 32 z 8 54 15 13 8 7 32 nrow 15 13 cws shadow b g r char craddr osd_en verd hord rdata l u m i n a n c e bsen shadow bsen o s d _ e n ch m c l k v ss (a) 1 4 v dd (a) and pll control 7 roms 6 mbus/spi adr 9 ch 6 x32b vpol hpol 10 vpol hpol control registers and data management memory x32b high resolution font 12 x 18
MC141545P2C 3 motorola absolute maximum ratings voltage referenced to v ss note: maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the electrical characteristics tables or pin description section. figure 1. switching characteristics symbol characteristic value unit v dd supply voltage ? 0.3 to + 7.0 v v in input voltage v ss ? 0.3 to v dd + 0.3 v id current drain per pin excluding v dd and v ss 10 ma ta operating temperature range 0 to 85 c t stg storage temperature range ? 65 to + 150 c recommended operating conditions symbol characteristic min typ max unit vdd supply voltage at pin 9, voltage referenced to pin16 vss. +4.75 ? +5.50 v vdd(a) supply voltage at pin 4, voltage referenced to pin16 vss. +4.75 ? +5.50 v t a ambient temperature range for operation 0 ? +80 c ac electrical characteristics (under recommended operating conditions) symbol characteristic min typ max unit t r t f output signal (r, g, b, fbkg and int) c load = 10 pf rise time fall time ? ? ? ? 4.5 4.5 ns ns f hflb hflb input frequency 29k ? 135k hz this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-imped- ance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appro- priate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. 90% 10% 90% 10% tf tr
MC141545P2C 4 motorola notes: for the m_bus can run at full speed and meet above specifiction, the hflb signal should be applied to pin5 not less than 60ms in advance of m_bus communication. this 60ms timing is for the stablizing of hsgmosd internal pll clk. figure 2. m_bus timing dc characteristics (under recommended operating conditions ) symbol characteristic min typ max unit v oh high level output voltage i out = ? 5 ma v dd ? 0.8 ? ? v v ol low level output voltage i out = 5 ma ? ? v ss + 0.4 v v il v ih digital input voltage (not including sda and scl) logic low logic high ? 0.7 v dd ? ? 0.3 v dd ? v v v il v ih input voltage of pin sda and scl in spi mode logic low logic high ? 0.7 v dd ? ? 0.3 v dd ? v v v il v ih input voltage of pin sda and scl in m_bus mode logic low logic high ? 0.7 v dd ? ? 0.3 v dd ? v v i ii high-z leakage current (r, g, b and fbkg) ? 10 ? + 10 m a i ii input current (not including rp, vco, r, g, b, fbkg and int) ? 10 ? + 10 m a i dd supply current (no load on any output) at vdd/vdda=5.0v ? ? + 26 ma m_bus ac timing (under recommended operating conditions) symbol characteristics min typ max unit f scl scl clock frequency(hflb frequency >= 29khz) ? ? 400 khz t buf bus free time between a stop and start condition 500 ? ? ns t hdsta start condition hold time 500 ? ? ns t low sck low period 400 ? ? ns t high sck high period 400 ? ? ns t susta start condition set-up time(for repeated start condition only) 100 ? ? ns t hddat data hold-time 250 ? ? ns t sudat data set-up time 100 ? ? ns t susto set-up time for stop condition 500 ? ? ns sda scl t buf t hdsta t sudat t high t low t hddat t susto t susta
MC141545P2C 5 motorola pin description vss(a) (pin 1) this pin provides the signal ground to the pll circuitry. an- alog ground for pll is separated from digital ground for opti- mal performance. vco (pin 2) a dc control voltage input to regulate an internal oscillator frequency. see the application diagram for the application values used. rp (pin 3) an external rc network is used to bias an internal vco to resonate at the specific dot frequency. the voltage at pin 3 should operate from 0.2v to 2.5v at any condition. see the application diagram for the application values used. v dd(a) (pin 4) a positive 5 v dc supply for pll circuitry. analog power for pll is separated from digital power for optimal performance. hflb (pin 5) this pin inputs a negative polarity horizontal synchronize signal pulse to phase lock into an internal system clock gener- ated by the on-chip vco circuit. the hflb signal input to this pin must be present during the bus communication. please also refer to "bus operation" section. ss (pin 6) this input pin is part of the spi system. an active low signal generated by the master device enables this slave device to accept data. pull high to terminate the spi communication. if m_bus is employed as the serial interface, this pin should be tied to either v dd or v ss . this pin is in high impedence state when the chip is being power down. sda (mosi) (pin 7) data and control message are being transmitted to this chip from a host mcu, via one of the two serial bus systems. with either protocol, this wire is configurated as a uni-directional data line. (detailed description of these two protocols will be discussed in the m_bus and spi sections). this pin is in high impedence state when the chip is being power down. scl (sck) (pin 8) a separate synchronizing clock input from the transmitter is required for either protocol. data is read at the rising edge of each clock signal. this pin is in high impedence state when the chip is being power down. v dd (pin 9) this is the power pin for the digital logic of the chip. vflb (pin 10) similar to pin 5, this pin inputs a negative polarity of vertical synchronize signal to synchronize the vertical control circuit. int (pin 11) this output pin is used to indicate the color intensity. if the intensity control bits are set in the row attribute registers or window control registers, this pin will output a logic high while displaying the specified windows or the characters on the associated rows. otherwise, it will keep in low state. please refer to figure 14 for detail timing chart. thus, 16-color selec- tion is achievable by combining this intensity pin with r/g/b outputs. on the other hand, this color intensity information could be reflected on the r/g/b pins by asserting tri-state instead of logic high if 3_s bit is set to 1. refer to the ?regis- ters? for more information. fbkg (pin 12) this pin will output a logic high while displaying characters or windows when fbkgc bit in frame control register is 0, and output a logic high only while displaying characters when fbkgc bit is 1. it is defaulted to high impedance state after power on, or when there is no output. an external 10 k w resis- tor pulled low is recommended to avoid level toggling caused by hand effect when there is no output. b,g,r (pin 13, 14, 15) hsgmosd-16 color outputs in cmos level to the host monitor. these three signals are open drain outputs if 3_state bit is set and the color intensity is inactive. other- wise, they are active high push-pull outputs. see ?regis- ters? for more information. these pins are in high impedance state after power on. v ss (pin 16) this is the ground pin for the digital logic of the chip. system description MC141545P2C is a full screen memory architecture. re- fresh is done by the built-in circuitry after a screenful of display data has been loaded in through the serial bus. only changes to the display data need to be input afterward. serial data, which includes screen mapping address, dis- play information, and control messages, are being transmitted via one of the two serial buses: m_bus or spi (mask option). these two sets of buses are multiplexed onto a single set of wires. standard parts offer m_bus transmission. data is first received and saved in the memory manage- ment circuit in the block diagram. meanwhile, the hsg- mosd-16 is continuously retrieving the data and putting it into a row buffer for display and refreshing, row after row. during this storing and retrieving cycle, a bus arbitration logic will patrol the internal traffic, to make sure that no crashes occur between the slower serial bus receiver and fast ?screen-refresh? circuitry. after the full screen display data is received through one of the serial communication interface, the link can be terminated if change on display is not required. the bottom half of the block diagram constitutes the heart of this entire system. it performs all the hsgmosd-16 func- tions such as programmable vertical length (from 16 lines to 63 lines), display clock generation (which is phase locked to the incoming horizontal sync signal at pin 5 hflb ), bordering or shadowing, and multiple windowing. communication protocols bus operation the operating clock for m_bus or spi bus derives from sys- tem dot clock. internal pll is using to generate the dot clock base on the hflb input frequency where the dot clock is equal to 384/768x hflb in 384/768 modes respectively. in or- der to have stable operation of m_bus or spi bus in the osd
MC141545P2C 6 motorola and meet below specifications, hflb must be presented and the pll locks to hflb properly. refer to application dia- gram for pll bias circuit. m_bus serial communication this is a two-wire serial communication link that is fully compatible with the iic bus system. it consists of sda bidirec- tional data line and scl clock input line. data is sent from a transmitter (master), to a receiver (slave) via the sda line, and is synchronized with a transmitter clock on the scl line at the receiving end. the maximum data rate is limited to 400 kbps.the default chip address is $7a. please refer to the iic-bus specification for detail timing requirement. operating procedure figure 3 shows the m_bus transmission format. the mas- ter initiates a transmission routine by generating a start condition, followed by a slave address byte. once the address is properly identified, the slave will respond with an ac- knowledge signal by pulling the sda line low during the ninth scl clock. each data byte which then follows must be eight bits long, plus the acknowledge bit, to make up nine bits together. appropriate row and column address informa- tion and display data can be downloaded sequentially in one of the three transmission formats described in data trans- mission formats section. in the cases of no ac- knowledge or completion of data transfer, the master will generate a stop condition to terminate the transmission rou- tine. note that the osd_en bit must be set after all the display information has been sent in order to activate the hsgmosd- 16 circuitry of MC141545P2C, so that the received informa- tion can then be displayed. figure 3. m_bus format serial peripheral interface (spi) similar to m_bus communication, spi requires separate clock (sck) and data (mosi) lines. in addition, a ss slave select pin is controlled by the master transmitter to initiate the receiver. operating procedure to initiate spi transmission, pull ss pin low by the master device to enable MC141545P2C to accept data. the ss input line must be a logic low prior to occurrence of sck and remain low until and after the last (eighth) sck cycle. after all data has been sent, the ss pin is then pulled high by master to terminate the transmission. data bit is sent from master to osd?s internal latch during rising edge of sck and then trans- mit to internal register during falling edge. therefore, last fall- ing edge of clk is needed for proper transmission of last byte data. no slave address is needed for spi. hence, row and column address information and display data (the data trans- mission formats are the same as in m_bus mode described in the previous section) can be sent immediately after the spi is initiated. figure 4. spi protocol data transmission formats after the proper identification by the receiving device, data train of arbitrary length is transmitted from the master. as mentioned above, two register blocks, display registers, attribute/control registers, need to be programmed before the proper operation. basically, these three areas use the similar transmission protocol. only two bits of the row/segment byte are used to distinguish the programming blocks. there are three transmission formats, from (a) to (c) as stated below. the data train in each sequence consists of row/seg address (r), column/line address (c), and data infor- mations (i). in format (a), each display information data have to be preceded with the corresponding row/seg address and column/line address. this format is particular suitable for updating small amount of data between different row. how- ever, if the current information byte has the same row/seg address as the one before, format (b) is recommended. for a full screen pattern change which requires massive informa- tion update or during power up situation, most of the row/seg and column/line address on either (a) or (b) format will appear to be redundant. a more efficient data transmission format (c) should be applied. it sends the ram starting row/ seg and column/line addresses once only, and then treat all subsequent data as data information. the row/seg and col- umn/line addresses will be automatically incremented inter- nally for each information data from the starting location. based on the different programming areas, the detail transmission protocol is described below respectively. (i) display register programming the data transmission formats are: (a) r - > c- > i -> r - > c - > i - > . . . . . . . . . (b) r - > c - > i - > c - > i - > c - > i. . . . . . . (c) r - > c - > i - > i - > i - > . . - > i dummy - > i dummy - > i - > i. . note: - r means row byte. - c means column byte. - i means data byte. - in format (c), two dummy data bytes(col 30, col 31)have to be inserted after the last data byte(col 29) at the end of each row, before the first data byte of the next row. data bytes ack stop condition ack chip address sda scl start condition 1 9 8 2?7 ss mosi msb lsb sck last byte first byte
MC141545P2C 7 motorola to differentiate the display row address from attribute area when transferring data, the most significant three bits are set to ?100? to represent display row address, while ?00x? for col- umn address used in format (a) or (b) and ?01x? for column address used in format (c). there is some limitation on using mix-formats during a single transmission. it is permissible to change the format from (a) to (b), or from (a) to (c), or from (b) to (a), but not from (c) back to (a) or (b). figure 5. data packet for display data figure 6. address bit patterns for display data (ii) attribute/control register programming the data transmission formats are similar with that in dis- play data programming: (a) r - > c- > i -> r - > c - > i - > . . . . . . . . . (b) r - > c - > i - > c - > i - > c - > i. . . . . . . (c) r - > c - > i - > i - > i - > . .- > i row attr. - > i dummy - > i - > i. . note: - r means row byte. - c means column byte. - i means data byte. - in format (c), one dummy data byte(col 31) has to be inserted after the row attribute data byte (col 30) at end of each row, before the first character attribute data byte of the next row. to differentiate the row address for attribute/control regis- ters from display area when transferring data, the most signif- icant three bits are set to ?101? to represent the row address of the attribute/control registers, while ?00x? for column address used in format (a) or (b) and ?01x? for column address used in format (c). there is some limitation on using mix-formats during a single transmission. it is permissible to change the format from (a) to (b), or from (a) to (c), or from (b) to (a), but not from (c) back to (a) or (b). figure 7. data packet for attribute/control data figure 8. address bit patterns for attribute/control data memory management all the internal programmable area can be divided into two parts including (1) display registers (2) attribute/control registers. please refer to the following two figures for the corresponding memory map. row addr col addr info address row column column x: don?t care d: valid data format bit 0 1 2 3 4 5 6 7 d d d d x 0 0 1 d d d d d x 0 0 d d d d d x 1 0 a, b a, b, c c display registers column 29 0 0 14 27 28 row addr col addr info address row column column x: don?t care d: valid data format bit 0 1 2 3 4 5 6 7 d d d d x 1 0 1 d d d d d x 0 0 d d d d d x 1 0 a, b a, b, c c character attribute registers 29 30 0 0 14 r o w r o w a t t r i b u t e r e g i s t e r s window 1 ~ window 4 frame crtl reg 15 0 11 12 20 27 28 window/frame control registers 31 18 reserved
MC141545P2C 8 motorola figure 9. memory map of display registers internal display ram are addressed with row and column (coln) number in sequence. as the display area is 15 rows by 30 columns, the related display registers are also 15 by 30. the space between row 0 and coln 0 to row 14 and coln 29 are called display registers, with each contains a character/ symbol address corresponding to display location on monitor screen. and each register is 8-bit wide to identify the selected character/symbol out of 256 rom fonts. figure 10. memory map of attribute/control registers besides the font selection, there is 3-bit attribute associ- ated with each symbol to identify its color and 3-bit to define its background. because of 3-bit attribute, each character can select any color out of 8 independently on the same row. as well as background. every data row associate with one attribute register, which locate at coln 30 of their respective rows, to control the characters display format of that row such as the character blinking, color intensity, character double height and character double width function. in addition, other control registers are located at row 15 such as window con- trol and frame function control registers. three window con- trol registers for each of four windows together with four frame control registers occupy the first 18 columns of row 15 space. these control registers will be described on the ?reg- isters? section. user should handle the internal display ram address loca- tion with care especially for those rows with double length alphanumeric symbols. for example, if row n is destined to be double height on the memory map, the data displayed on screen row n and n+1 will be represented by the data con- tained in the memory address of row n only. the data of next row n+1 on the memory map will appear on the screen of n+2 and n+3 row space and so on. hence, it is not necessary to throw in a row of blank data to compensate for the double row action. user needs to take care of excessive row of data in memory in order to avoid over running the limited number of row space on the screen. there is difference for rows with double width alphanu- meric symbols. only the data contained in the even num- bered columns of memory map will be shown, the odd numbered columns will be ignored and not disclosed. registers (i) display register display register (row 0~14, coln 0~29) bit 7-0 craddr - this eight bits address one of the 256 characters or symbols resided in the character rom fonts. (ii) attribute/window/control/frame registers character attribute register (row 0~14, coln 0~29) bit 6-4 these three bits define the color of the back- ground for the correspondent characters. if all three bits are clear, no background will be shown(transparent). therefore, total seven background colors can be selected. bit 3 blink - the blinking effect will be active on the corresponding character if this bit is set to 1. the blinking fre- quency is approximately one time per second (1hz) with fifty- fifty duty cycle at 80hz vertical scan frequency. display registers column 29 0 0 14 r o w 27 28 character attribute registers column 29 30 0 0 14 r o w r o w a t t r i b u t e r e g i s t e r s window 1 ~ window 4 frame crtl reg 15 0 11 12 20 27 28 window/frame control registers 31 18 reserved 0 1 2 3 4 5 6 7 craddr 0 1 2 3 4 5 6 7 b g r blink bgr bgg bgb
MC141545P2C 9 motorola bit 2-0 these three bits are the color attribute to define the color of the associated character/symbol. row attribute register (row 0~14, coln 30) bit 2 r_int - row intensity bit controls the color inten- sity of the displayed character/symbol on the corresponding row. setting this bit to 1 means high intensity color and the int pin will go high while displaying the characters of this row. bit 1 chs - it determines the height of a display symbol. when this bit is set, the symbol is displayed in double height. bit 0 cws - similar to bit 1, character is displayed in double width, if this bit is set. window 1 registers row 15 coln 0 row 15 coln 1 bit 2 wen - it enables the window 1 generation if this bit is set. bit 1 w_int - this additional color related bit provides the color intensity selection for window 1. if this bit is 0, int pin will go low while displaying window 1.the default value is 1 to indicate high intensity. .video pre-amplifier or external r/ g/b switch can make use of int pin for windows?s color intensity control. bit 0 w_shd - shadowing on window. set this bit to activate the window 1 shadowing. when the window is active, the right m pixels and lower n horizontal scan lines will output black shadowing. the width/height of window shadow, num- ber of m/n, is defined in the frame control registers located at row 15 column 16 and 17. see the following figure and the related frame control register for detail. row 15 coln 2 bit 2-0 r, g and b - controls the color of window 1. refer to table 1 for color selection. window 1 registers occupy col- umn 0-2 of row 15, window 2 from column 3-5, window 3 from 6-8 and window 4 from 9-11. window 1 has the highest priority, and window 4 the least. if window over-lapping occurs, the higher priority window will cover the lower one, and the higher priority color will take over on the overlap win- dow area. if the start address is greater than the end address, this window will not be displayed. window 2 registers row 15 coln 3 row 15 coln 4 bit 2 wen - it enables the window 2 generation if this bit is set. bit 1 w_int - this additional color related bit provides the color intensity selection for window 2. if this bit is 0, int pin will go low while displaying window 2.the default value is 1 to indicate high intensity. .video pre-amplifier or external r/ g/b switch can make use of int pin for windows?s color intensity control. table 1. the character/window color selection r g b black 0 0 0 blue 0 0 1 green 0 1 0 cyan 0 1 1 red 1 0 0 magenta 1 0 1 yellow 1 1 0 white 1 1 1 0 1 2 3 4 5 6 7 cws chs r_int 0 1 2 3 4 5 6 7 row end addr msb lsb row start addr msb lsb coln 0 row 15 wen w_int col start addr msb lsb coln 1 0 1 2 3 4 5 6 7 row 15 w_shd window shadowing n horizontal lines m pixels m pixels window area n horizontal lines m and n are defined in the frame control registers located at row 15 column 16 note: and column 17. r g col end addr msb lsb coln 2 0 1 2 3 4 5 6 7 b row 15 0 1 2 3 4 5 6 7 row end addr msb lsb row start addr msb lsb coln 3 row 15 coln 4 row 15 wen w_int col start addr msb lsb 0 1 2 3 4 5 6 7 w_shd
MC141545P2C 10 motorola bit 0 w_shd - shadowing on window. set this bit to activate the window 2 shadowing. row 15 coln 5 bit 2-0 r, g and b - controls the color of window 2.refer to table 1 for color selection. window 1 registers occupy col- umn 0-2 of row 15, window 2 from column 3-5, window 3 from 6-8 and window 4 from 9-11. window 1 has the highest priority, and window 4 the least. if window over-lapping occurs, the higher priority window will cover the lower one, and the higher priority color will take over on the overlap win- dow area. if the start address is greater than the end address, this window will not be displayed. window 3 registers row 15 coln 6 row 15 coln 7 bit 2 wen - it enables the window 3 generation if this bit is set. bit 1 w_int - this additional color related bit provides the color intensity selection for window 3. if this bit is 0, int pin will go low while displaying window 3.the default value is 1 to indicate high intensity. .video pre-amplifier or external r/ g/b switch can make use of int pin for windows?s color intensity control. bit 0 w_shd - shadowing on window. set this bit to activate the window 3 shadowing. row 15 coln 8 bit 2-0 r, g and b - controls the color of window 3.refer to table 1 for color selection. window 1 registers occupy col- umn 0-2 of row 15, window 2 from column 3-5, window 3 from 6-8 and window 4 from 9-11. window 1 has the highest priority, and window 4 the least. if window over-lapping occurs, the higher priority window will cover the lower one, and the higher priority color will take over on the overlap win- dow area. if the start address is greater than the end address, this window will not be displayed. window 4 registers row 15 coln 9 row 15 coln 10 bit 2 wen - it enables the window 4 generation if this bit is set. bit 1 w_int - this additional color related bit provides the color intensity selection for window 4. if this bit is 0, int pin will go low while displaying window 4.the default value is 1 to indicate high intensity. video pre-amplifier or external r/ g/b switch can make use of int pin for windows?s color intensity control. bit 0 w_shd - shadowing on window. set this bit to activate the window 4 shadowing. row 15 coln 11 bit 2-0 r, g and b - controls the color of window 4.refer to table 1 for color selection. window 1 registers occupy col- umn 0-2 of row 15, window 2 from column 3-5, window 3 from 6-8 and window 4 from 9-11. window 1 has the highest priority, and window 4 the least. if window over-lapping occurs, the higher priority window will cover the lower one, and the higher priority color will take over on the overlap win- dow area. if the start address is greater than the end address, this window will not be displayed. vertical delay control register row 15 coln 12 bit 7-0 vertd - these 8 bits define the vertical starting position. total 256 steps, with an increment of four horizontal lines per step for each field. its value can?t be zero anytime. the default value of it is 4. horizontal delay control register row 15 coln 13 r g col end addr msb lsb coln 5 0 1 2 3 4 5 6 7 b row 15 0 1 2 3 4 5 6 7 row end addr msb lsb row start addr msb lsb coln 6 row 15 coln 7 row 15 wen w_int col start addr msb lsb 0 1 2 3 4 5 6 7 w_shd r g col end addr msb lsb coln 8 0 1 2 3 4 5 6 7 b row 15 0 1 2 3 4 5 6 7 row end addr msb lsb row start addr msb lsb coln 9 row 15 wen w_int col start addr msb lsb coln 10 0 1 2 3 4 5 6 7 row 15 w_shd r g col end addr msb lsb coln 11 0 1 2 3 4 5 6 7 b row 15 0 1 2 3 4 5 6 7 lsb row 15 msb vertd coln 12 0 1 2 3 4 5 6 7 lsb row 15 msb hord coln 13 clr
MC141545P2C 11 motorola bit 7 clr - setting this bit to 1 clear all display register from row 0 to row 14; control register will not be erased. bit 6-0 hord - horizontal starting position for character display. 7 bits give a total of 128 steps and each increment represents five dots movement shift to the right on the moni- tor screen. its value cannot be zero anytime. the default value of it is 15. character height control register row 15 coln 14 bit 7 hf - high frequency bit. if the incoming h sync signal is higher than 60 khz, set this bit to 1 for better perfor- mance. this bit controls gain of internal vco so that pll can work for whole range from up to 135khz. bit 6 bit reserved. set to 0 for normal operation. bit 5-0 ch5-ch0 - this six bits will determine the dis- played character height. hsgmosd adopts 12 by 18 font matrix and the middle 16 lines, line 2 to line 17, are expanded by brm algorithm. the top line and bottom line will be dupli- cated dependent on the value of ch. no any line is dupli- cated for top and bottom if ch is less than 32. one extra duplicated line will be inserted for top and bottom if ch is larger or equal to 32 and less than 48. two extra duplicated lines will be inserted for top and bottom if ch is larger or equal to 48. setting a value below 16 will not have a predict- able result. display character line number is equal to c1 x (18 + c2) where c1 = 1, 2 or 3 defined by ch5-ch4 and c2 = 0-15 defined by ch3-ch0 (brm). figure 11. variable character height figure 11 illustrates the enlargement algorithm for top and bottom lines and how this chip expand the built-in character font to the desired height. in this approach, the actual character height in unit of the scan line can be calculated from the following simple equa- tion: h = ch + n where h is the expanded character height in unit of lines ch is the number defined by ch5 ~ ch0 n is a variable dependent on the value of ch n = 2 when 16 < ch<32 n = 4 when 32 < ch<48 n = 6 when 48 < ch<64 7 row 15 6 5 4 3 2 1 0 ch5 ch4 ch3 ch2 ch1 ch0 coln 14 hf 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 18 lines 24 lines 38 lines 27 lines built-in font display character when ch=22 display character when ch=34 when ch=25 display character (12x18 matrix) when ch=16 16 17 (1+16+1) (1+25+1) (1+22+1) (2+34+2) ch lines 3 lines ch lines 2 lines 3 lines 1 line ch lines 1 line 2 lines 16 < ch<32 32 < ch<48 48 < ch<64 character enlargement (16~31) (32~47) (48~63)
MC141545P2C 12 motorola frame control register row 15 coln 15 bit 7 osd_en - osd circuit is activated when this bit is set. bit 6 bsen - it enables the character bordering or shad- owing function when this bit is set. bit 5 shadow - character with black-edge shadowing is selected if this bit is set, otherwise bordering prevails. bit 3 x32b - it determines the number of dots per hori- zontal line. there are 384 dots per horizontal line if bit x32b is clear and this is also the default power on state. otherwise, 768 dots per horizontal sync line when bit x32b is set to 1. please refer to the table 2 for details. bit 2 3_s - by setting this bit to 1, r/g/b could output high impedance state if the intensity attribute of characters or windows is set to 0. it means the corresponding r/g/b out- put will go high impedance instead of driving-high while dis- playing the low intensity characters or windows. after power on, this bit is reset and the r/g/b are push-pull outputs ini- tially. bit 1 fan - it enables the fan-in/fan-out functions when osd is turned on from off state or vice versa. if this bit is set, it roughly takes about one second to fully display the whole menu. it also takes 1 second to disappear completely. bit 0 fbkgc - it determines the configuration of fbkg output pin. when it is clear. fbkg pin outputs high during displaying characters or windows. otherwise, fbkg pin out- puts high only during displaying characters. figure 12. character bordering and shadowing frame control register row 15 coln 16 bit 7-6 ww41, ww40 - it determines the shadow width of the window 4 when the window shadowing function is acti- vated. please refer to the following table for more details where m is the actual pixel number of the shadowing. table 2. resolution setting x32b 0 1 dots / line 384 768 resolution cga svga 7 osd_en row 15 6 5 4 3 2 1 0 bsen shadow fbkgc x32b coln 15 fan 3_s table 3. shadow width setting (ww41, ww40) (0, 0) (0, 1) (1, 0) (1, 1) shadow width m (unit in pixel) 2 4 6 8 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 bordering 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 shadowing window shadowing n horizontal lines m pixels m pixels window area n horizontal lines m and n are defined in the frame control registers located at row 15 column 16 note: and column 17 7 row 15 6 5 4 3 2 1 0 coln 16 ww20 ww21 ww10 ww11 ww40 ww41 ww30 ww31
MC141545P2C 13 motorola bit 5-4 ww31, ww30 - similarly as ww41, ww40, these two bits determine the shadow width of the window 3 when the window shadowing function is activated. bit 3-2 ww21, ww20 - similarly as ww41, ww40, these two bits determine the shadow width of the window 2 when the window shadowing function is activated. bit 1-0 ww11, ww10 - similarly as ww41, ww40, these two bits determine the shadow width of the window 1 when the window shadowing function is activated frame control register row 15 coln 17 bit 7-6 wh41, wh40 - it determines the shadow height of the window 4 when the window shadowing function is acti- vated. please refer to the following table for more details where n is the actual line number of the shadowing. bit 5-4 wh31, wh30 - similarly as wh41, wh40, these two bits determine the shadow height of the window 3 when the window shadowing function is activated. bit 3-2 wh21, wh20 - similarly as wh41, wh40, these two bits determine the shadow height of the window 2 when the window shadowing function is activated. bit 1-0 wh11, wh10 - similarly as wh41, wh40, these two bits determine the shadow height of the window 1 when the window shadowing function is activated. frame control register row 15 coln 18 bit 7-3 rspace - these 5 bits define the row to row spac- ing in unit of horizontal scan line. it means extra n lines, defined by this 5-bit value, will be appended for each display row. because of the nonuniform expansion of brm used by character height control, this register is usually used to main- tain the constant osd menu height for different display modes instead of adjusting the character height. the default value of it is 0. it means there is no any extra line inserted between row and row after power on. it can be used for por- trait monitor too when icon design is rotated 90 degree. bit 2 tric - tri-state control. this bit is used to control the driving state of output pins, r, g, b and fbkg when the osd is disabled. after power on, this bit is reset and r, g, b and fbkg are in high impedance state while osd being dis- abled. if it is set by mcu, these four output pins will drive low while osd being in disabled state. basically, the setting is dependent on the requirement of the external application cir- cuit. bit 1 hpol - this bit selects the polarity of the incoming horizontal sync signal ( hflb ). if it is negative polarity, clear this bit. otherwise, set this bit to 1 to represent the positive h sync signal. after power on, this bit is cleared. bit 0 vpol - this bit selects the polarity of the incoming vertical sync signal ( vflb ). if it is negative polarity, clear this bit. otherwise, set this bit to 1 to represent the positive v sync signal. after power on, this bit is cleared. ? note: the registers located at column 19 of row 15 are reserved for the chip testing. in normal operation, they should not be programmed anytime. a software called hsgmosd-16 font editor in ibm pc environment was written for MC141545P2C editing pur- poses. it generates a set of s-record or binary record for the desired display patterns to be masked onto the character rom of the MC141545P2C. in order to have better character display within windows, we suggest you to place your designed character font in the centre of the 12x18 matrix, and let its spaces be equally located in the four sides of the matrix. the character $00 is pre-defined for blank character, the character $ff is pre- defined for full-filled character. in order to avoid submersion of displayed symbols or char- acters into a background of comparable colors, a feature of bordering which encircles all four sides, or shadowing which encircles only the right and bottom sides of an individual dis- play character is provided. figure 12 shows how a character is being jacketed differently. to make sure that a character is bordered or shadowed correctly, at least one dot blank should be reserved on each side of the character font. frame format and timing figure 13 illustrates the positions of all display characters on the screen relative to the leading edge of horizontal and vertical flyback signals. the shaded area indicates the area not interfered by the display characters. notice that there are two components in the equations stated in figure 13 for hori- zontal and vertical delays: fixed delays from the leading edge of hflb and vflb signals, regardless of the values of hord and vertd: (47 dots + phase detection pulse width) and one h scan line for horizontal and vertical delays, respectively; variable delays determined by the values of hord and vertd. refer to frame control registers coln 9 and 10 for the definitions of vertd and hord. phase detection pulse width is a function of the external charge-up resistor, which is the 1m w resistor in a series with 10 k w to vco pin in the application diagram. dot frequency is determined by the equation: h freq. x 384 if the bit x32b is clear and h freq. x 768 if bit x32b is set to 1. for example, dot frequency is 12.28 mhz if h freq is 32 khz while bit x32b is 0. if x32b is 1, the dot frequency will be 24.57 mhz (double of the original one). when double character width is selected for a row, only the even-numbered characters will be displayed, as shown in row 2. notice that the total number of horizontal scan lines in the display frame is variable, depending on the chosen character height of each row. care should be taken while configuring each row character height so that the last horizontal scan line in the display frame always comes out before the leading edge of vflb of next frame to avoid wrapping display charac- ters of the last few rows in the current frame into the next table 4. shadow width setting (wh41, wh40) (0, 0) (0, 1) (1, 0) (1, 1) shadow height n (unit in line) 2 4 6 8 7 row 15 6 5 4 3 2 1 0 coln 17 wh20 wh21 wh10 wh11 wh40 wh41 wh30 wh31 7 row 15 6 5 4 3 2 1 0 vpol coln 18 hpol tric msb lsb rspace
MC141545P2C 14 motorola frame. the number of display dots in a horizontal scan line is always fixed at 360, regardless of row character width and the setting of bit x32b. although there are 30 character display registers that can be programmed for each row, not every programmed charac- ter can be shown on the screen in 384 dots resolution. usual- ly, only 24 characters can be shown in this resolution at most. this is induced by the retrace time that is required to retrace the h scan line. in other resolution, 768dots, 30 characters can be displayed on the screen totally if the horizontal delay register is set properly. figure 14 illustrates the timing of all output signals as a function of window and fast blanking features. line 3 of all three characters is used to illustrate the timing signals. the shaded area depicts the window area. both the left hand side and right hand side characters are embodied in a window with only one difference: fbkgc bit. the middle character does not have a window as its background. timing of signal fbkg depends on the configuration of fbkgc bit. the configuration of fbkgc bits affects only fbkg signal timing. waveform ?r, g or b?, which is the actual waveform at r, g, or b pin, is the logical or of waveform ?character r, g or b? and waveform ?window r, g or b?. ?character r, g, or b? and ?window r, g, or b? are internal signals for illustration purpose only. figure 13. display frame format vflb h f l b 1 r o w c o l u m n 2 3 4 5 6 . . . . . . 1 4 1 2 3 0 0 2 9 2 8 2 7 2 6 d o u b l e h e i g h t d o u b l e w i d t h c h 5 - 0 = 0 x 2 1 c h 5 - 0 = 0 x 2 1 & d o u b l e h e i g h t s t a n d a r d s i z e 1 2 x 1 8 & d o u b l e w i d t h c o l 0 c o l 2 c o l 4 c o l 6 c o l 8 c o l 1 0 c o l 1 2 c o l 1 4 c o l 2 8 1 2 x 3 0 d o t s f i x e d variable number of hscan lines vertical delay = vertd x 4 + 1 h scan lines h o r i z o n t a l d e l a y = ( h o r d x 5 + 4 7 ) d o t s + p h a s e d e t e c t i o n p u l s e w i d t h d i s p l a y f r a m e f o r m a t a r e a n o t i n t e r f e r e d b y d i s p l a y c h a r a c t e r s d i s p l a y c h a r a c t e r . . . . . . . . . . . . . . . . h f l b
MC141545P2C 15 motorola figure 14. timing of output signals font MC141545P2C contains 256 character/symbol fonts including 240 normal fonts and 16 multi-color fonts. the nor- mal fonts are located from number $00 to $ef . the 16 multi- color fonts occupy number $f0 to $ff and their patterns can be designed using font editor. see the figures on the next page for the details fonts mapping. multi-color font the color fonts comprises three different r, g, and b fonts. when the code of color font is accessed, the separate r/g/b dot pattern is output to the correspondig r/g/b output. see figure 15 for the sample displayed color font. no black color can be defined in color font: black window underline the color font can make the dots(rgb=000) become black in color. it has to be consider during font design stage. figure 15. example of multi-color font f b k g w _ i n t = 0 & f b k g c b i t = 0 c h a r a c t e r i n s i d e a w i n d o w c h a r a c t e r o u t s i d e a w i n d o w w _ i n t = 1 & f b k g c b i t = 1 c h a r a c t e r i n s i d e a w i n d o w 3 t i m i n g o f o u t p u t s i g n a l s a s a f u n c t i o n o f w i n d o w , f b k g c b i t a n d r o w i n t e n s i t y f e a t u r e s l i n e 3 w i n d o w r , g o r b c h a r a c t e r r , g o r b r , g o r b i n t ( r o w i n t e n s i t y = 1 f o r t h i s r o w ) r g b magenta green glue cyan
MC141545P2C 16 motorola icon combination user can create on-screen menu based on those charac- ters and icons. address $00 & $ef are pre-defined characters for testing. rom content figures 19 ? 22 show the rom content of mc141545p2. mask rom is optional for custom parts. table 6. combination map table 5. the multi-color font color selection r g b background color 0 0 0 blue 0 0 1 green 0 1 0 cyan 0 1 1 red 1 0 0 magenta 1 0 1 yellow 1 1 0 white 1 1 1 icon rom address(hex) arabic numerals 08-11 alphabet 12-2d european 2e-48 japanese 49-81 symbols 01-07, 82-c4 geometry c5-ee color f0-ff
MC141545P2C 17 motorola figure 16. rom $00 - $3f 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f
MC141545P2C 18 motorola figure 17. rom $40 - $7f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f
MC141545P2C 19 motorola figure 18. rom $80-$bf 80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f 90 91 92 93 94 95 96 97 98 99 9a 9b 9c 9d 9e 9f a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf
MC141545P2C 20 motorola figure 19. rom $c0 - $ff c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef
MC141545P2C 21 motorola design considerations distortion motorola?s MC141545P2C has a built-in pll for multisys- tems application. pin 2 voltage is a dc basing for the internal vco in the pll. when the input frequency (hflb) in pin 5 becomes higher, the vco voltage will increase accordingly. the built-in pll then has a higher locked frequency output. the frequency should be equal to 384/768 x hflb (depends on resolution). it is the dot-clock in each horizontal line. display distortion is caused by noise in pin 2. positive noise makes vco run faster than normal. the corresponding scan line will be shorter accordingly. in contrast, negative noise causes the scan line to be longer. the net result will be distortion on the display, especially on the right hand side with window turn on. in order to have distortion-free display, the following rec- ommendations should be considered. only analog part grounds (pin 2 to pin 4) can be connect- ed to pin 1(v ss(a) ). v ss and other grounds should con- nect to pcb common ground. then the v ss(a) and v ss grounds can be connected by a bead core. please refer to the application diagram(note: vss(a) and vss are con- nected internally.) dc supply path for pin 4 (v dd(a) ) should be separated from other switching devices. lc filter should be connected between pin 9 and pin 4. refer to the values used in the application diagram. biasing and filter networks should be connected to pin 2 and pin 3. refer to the recommended networks in the ap- plication diagram. two small capacitors can be added between pin1-pin2 and pin3-pin4 to filter vco noise if necessarry. values should be small enough to avoid picture unlocking caused by temperature variation. a bead core can be added after pin4 vdda(the 0.33uh shown in diagram) to filter power noise if necessary. jittering and unlocking most display jittering and unlocking is caused by hflb in pin 5. care must be taken if the hflb signal comes from the flyback transformer. a short path and shielded cable are rec- ommended for a clean signal. buffer is needed for both hflb and vflb inputs. refer to the value used in the application diagram. note:the bead core added between v ss(a) and v ss can also enhance the osd stability in high frequency hflb oper- ation . display dancing most display dancing is caused by interference of the se- rial bus. it can be avoided by adding resistors in the bus in series. application diagram 0.1 100 m h 0.1 m f 100 m f 1.8 k v cc 10 9 16 15 14 13 12 11 10 1 2 3 4 5 6 7 8 2200pf 100 100 100 v dd v ss r g b fbkg int vflb v ss(a) vco rp hflb ss sda(mosi) scl(sck) v dd(a) hflb 15 k vflb int fbkg b g r 1m digital ground - common analog digital ground hsgmosd-16 iic(spi) bus 10 k vcc 470 vcc 470 buffer buffer v ss(a) and v ss are connected internally * * *small capacitors and bead or power noise(optional). **5.6 m h bead core added to remove distortion and enhance osd stability at high frequency. * * * 0.33 m h cmos level rgb output core added to filter vco *
MC141545P2C 22 motorola package dimensions p suffix plastic package(dual in-line package) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold -a- b f c s h g d j l m 16 pl seating 1 8 9 16 k plane -t- a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 m
MC141545P2C 23 motorola motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the applicatio n or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? param eters can and do vary in different applications. all operating parameters, including ?typicals? must be validated for each customer application by customer?s tech nical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or autho rized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola p roducts for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affil iates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer.

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